Copper metallization is increasingly being used for advanced semiconductor device integrated circuit fabrication including semiconductor features having sub-quarter micron linewidths and high aspect ratios to larger features such as bonding pads. Copper and its alloys have lower resistivity and better electromigration resistance compared to other metals such as, for example, aluminum. These characteristics are critical for achieving device reliability together with higher current densities and increased signal propagation speed. While several processing difficulties related to forming copper semiconductor features have been overcome, several problems remain, including the problem of barrier layer integrity formed over low-K porous dielectric insulating layers and the consequent tendency of metals, for example copper, to penetrate and electro-migrate through the dielectric insulating layer.
Low-K porous dielectric insulating layers are increasingly used in forming smaller, high speed devices. Porosity is intentionally introduced into dielectric insulating layers by various methods in order to reduce the dielectric constant of the material and thereby increase the electrical signal transport speed. As device sizes continue to shrink, the level of porosity introduced into the low-K material has increased to further decrease the dielectric constant. Co-extensively with the evolution of smaller devices including metal interconnect lines, barrier layers lining an etched metal interconnect opening have been commonly used to prevent penetration and electro-migration of the metal, for example copper, used to fill the metal interconnect.
One increasing problem with prior art methods of forming barrier layers, for example refractory metals and metal nitrides, is achieving adequate coverage of the barrier layers over the low-K material. For example, as device sizes decreases, scaling considerations also require thinner barrier layers. The coextensive requirements of thinner barrier layers and more porous low-K dielectric insulating layers has led to problems with the integrity of barrier layers, frequently leading to metal electromigration, and subsequent device degradation.
Thus, there is a continuing need for novel semiconductor micro-circuitry manufacturing methods to improve the electrical performance of metal interconnect features including improved manufacturing methods to improved barrier layer integrity while reducing manufacturing cycle times.
It is therefore among the objects of the invention to provide a method to improve the electrical performance of metal interconnect features including improved manufacturing methods to improved barrier layer integrity while reducing manufacturing cycle times, in addition to overcoming other shortcomings of the prior art.